A Power-efficient 32bit ARM ISA Processor using Timing- error Detection and Correction for Transient-error Tolerance and Adaptation to PVT Variation

Razor [1-3] is a hybrid technique for dynamic detection and correction of timing errors. A combination of error detecting circuits, and micro-architectural recovery mechanisms creates a system which is robust in the face of timing errors, and can be tuned to an efficient operating point by dynamically eliminating unused guardbands. Canary or tracking circuits [4-5] can compensate for certain manifestations of PVT variation, however they still require substantial margining to account for fast-moving or localized events, such as Ldi/dt, local IR drop, capacitive coupling, or PLL jitter. These types of events are often transient, and while the pathological case of all occurring simultaneously is extremely unlikely, it cannot be ruled out. A Razor system can survive both fast-moving and transient events, and adapt itself to the prevailing conditions, allowing excess margins to be reclaimed. The savings from margin reclamation can be realized either as a per device power efficiency (higher throughput same VDD, same throughput lower power), or as parametric yield improvement for a batch of devices. Error-detection in Razor is performed by specific circuits which explicitly check for late arriving signals. Error correction is performed by the system using either stall mechanisms with 2 corrected data substitution, or by instruction/transaction-replay. Measurements on a simplified Alpha pipeline[2] showed 33% energy savings. In [3], the authors evaluated error detection circuits on a 3-stage pipeline, using artificially induced Vcc droops showing 32% throughput (TP) gain at same Vcc, or 17% Vcc reduction at equal TP. This paper presents Razor applied to a processor which has timing paths that are representative of an industrial design, running at frequencies over 1GHz, where fast moving and transient timing-related events are significant.. The processor implements a subset of the ARM ISA, with a micro-architecture design which has balanced pipeline stages resulting in critical memory access, and clock gating enable paths. The design has been fabricated on a UMC[6] 65nm process, using industry standard EDA tools, with a worst case STA signoff of 724MHz. Silicon measurements on 63 samples including split lots show a 52% power reduction of the overall distribution for 1GHz operation. Error-rate driven dynamic voltage (DVS) and frequency scaling (DFS) schemes have been evaluated. The micro-architecture is shown in (Fig. 1). The pipeline is balanced using a combination of up-front micro-architecture design and the low level path equalization performed by backend tools, such that all stages have very similar critical-path delay. The pipeline is …